View MAX8597_3684784.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX8597/max8598/max8599 voltage-mode pwm step-down controllers are designed to operate from a 4.5v to 28v input supply and generate output voltages down to 0.6v. a proprietary switching algorithm stretch- es the duty cycle to >99.5% for low-dropout design. unlike conventional step-down regulators using a p- channel high-side mosfet to achieve high duty cycle, the MAX8597/max8598/max8599 drive n-channel mosfets resulting in high efficiency and high-current- capability designs. the MAX8597 is available in a 20-pin thin qfn pack- age and is designed for applications that use an analog signal to control the output voltage with an adjustable offset, such as dc fan-speed control. this is achieved with an internal uncommitted operational amplifier. the MAX8597 is also targeted for tracking output-voltage applications for chipsets, asic and dsp cores, and i/o supplies. the max8598/max8599 are available in a 16- pin thin qfn package and do not have the uncommitted operational amplifier, reference input, and reference out- put, but offer an open-drain, power-ok output. the MAX8597/max8598/max8599 allow startup with prebias voltage on the output for applications where a backup supply or a tracking device may charge the output capacitor before the MAX8597/max8598/ max8599 are enabled. in addition, the max8599 fea- tures output overvoltage protection. these controllers also feature lossless high-side peak inductor current sensing, adjustable current limit, and hiccup-mode short-circuit protection. switching fre- quency is set with an external resistor from 200khz to 1.4mhz. this wide frequency range combined with a wide-bandwidth error amplifier enables the loop com- pensation scheme to give the user ample flexibility to optimize for cost, size, and efficiency. applications nonisolated power modules variable-speed dc fan power supplies (MAX8597) tracking power supplies (MAX8597) chipset power supplies features ? low dropout with >99.5% duty cycle ? lossless high-side current limit ? wide 4.5v to 28v input range ? dynamic output voltage adjustment with adjustable offset (MAX8597) ? remote voltage sensing for both positive and negative rails (MAX8597) ? tracking output through refin (MAX8597) ? adjustable switching frequency from 200khz to 1.4mhz ? adjustable soft-start ? prebias startup ? enable and power-ok (max8598/max8599) for flexible sequencing ? 25mhz error amplifier ? adjustable hiccup current limit for output short-circuit protection ? output overvoltage protection (max8599) ? small, low-profile thin qfn package MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ________________________________________________________________ maxim integrated products 1 1 avl 2 refin 3 gnd 4 ss 5 fb 15 lx 14 dh 13 bst 12 pgnd 11 dl 6 comp 7 en 8 refout 9 v+ 10 vl 20 ain+ 19 ain- 18 aout 17 freq 16 ilim MAX8597 thin qfn 4mm x 4mm top view pin configurations ordering information 19-3505; rev 0; 11/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX8597 etp+ -40? to +85? 20 thin qfn 4mm x 4mm (t2044-3) max8598 ete+ -40? to +85? 16 thin qfn 4mm x 4mm (t1644-4) max8599 ete+ -40? to +85? 16 thin qfn 4mm x 4mm (t1644-4) + denotes lead-free package. pin configurations continued at end of data sheet
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v v+ = v vl = v avl = v en = v refin = 5v, v bst = 6v, v lx = 1v, c vl = 4.7?, c refout = 1?, v ain- = v aout , v ain+ = 2.5v, v ilim = v lx - 0.2v, v fb = 0.65v, gnd = pgnd = 0v, c ss = 0.01?, r freq = 20k ? , t a = 0? to +85? , typical values are at t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+, ilim to gnd .....................................................-0.3v to +30v avl, vl to gnd........................................................-0.3v to +6v pgnd to gnd .......................................................-0.3v to +0.3v fb, en, pok, ain-, ain+, refin to gnd ................-0.3v to +6v aout, refout, freq, ss, comp to gnd .....................................................-0.3v to (v avl + 0.3v) bst to gnd ............................................................-0.3v to +36v dh to lx ....................................................-0.3v to (v bst + 0.3v) lx to gnd ........................-2v (-2.5v for less than 50ns) to +30v lx to bst..................................................................-6v to +0.3v dl to pgnd.................................................-0.3v to (v vl + 0.3v) continuous power dissipation 16- or 20-pin thin qfn up to +70? (derate 16.9mw/? above +70?)........1349mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65 c to +150? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units general v+ operating range 5.5 28.0 v v+/vl operating range v+ = vl 4.5 5.5 v v+ operating supply current v v+ = 12v, vl unloaded, no mosfets connected, v fb = 0v 3.4 5.0 ma v+ standby supply current v v+ = 12v, vl unloaded, v fb = 0v 2.0 ma vl regulator output voltage 5.5v < v v+ < 28v, 1ma < i load < 35ma 4.7 5.0 5.3 v vl undervoltage-lockout trip level rising edge, typical hysteresis = 460mv 4.05 4.2 4.35 v thermal shutdown rising temperature, typical hysteresis = 10? +160 ? reference (MAX8597 only) refout output voltage i refout = 150?, v v+ = v vl = 4.5v or 5.5v 2.49 2.50 2.51 v refout load regulation i refout = 10? to 1ma 10 mv refout internal discharge switch on-resistance during vl uvlo 15 ? current-limit comparator (all current limits are tested at v v+ = v vl = 4.5v and 5.5v) ilim sink current 1.8v < v lx < 28v, v bst = v lx + 5v 180 200 220 ? comparator input offset voltage error v lx = 28v, v bst = v lx + 5v -10 +10 mv soft-start soft-start source current v ss = 100mv 3 5 7 ? soft-start sink current v ss = (0.6v or v refin ) 3 5 7 ? frequency r freq = 100k ? 150 200 240 r freq = 20.0k ? 800 1000 1200 frequency r freq = 14.3k ? 1100 1400 1700 khz
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v v+ = v vl = v avl = v en = v refin = 5v, v bst = 6v, v lx = 1v, c vl = 4.7?, c refout = 1?, v ain- = v aout , v ain+ = 2.5v, v ilim = v lx - 0.2v, v fb = 0.65v, gnd = pgnd = 0v, c ss = 0.01?, r freq = 20k ? , t a = 0? to +85? , typical values are at t a = +25?, unless otherwise noted.) parameter conditions min typ max units dh minimum off-time 180 200 220 ns dh minimum on-time 115 140 ns fb error amplifier fb input bias current 100 na fb input voltage set point over load and line 0.594 0.600 0.606 v fb offset error v refin = 1.25v and 2.5v, measured with respect to refin +10 -10 mv error-amp open-loop voltage gain v comp = 1.2v to 2.4v 72 90 db slew rate c load = 80pf 18 v/? uncommitted operational amplifier (MAX8597 only) r load = 100k ? 90 open-loop voltage gain (a vol ) r load = 10k ? 70 db output-voltage swing high v ain+ = 2.5v, v ain - = (v ain+ - 100mv), i source = 100? v avl - 20mv v output-voltage swing low v ain+ = 2.5v, v ain - = (v ain+ + 100mv), i sink = 100? 20 mv unity-gain bw 1.5 mhz c load = 10pf, r load = 10k ? to 100k ? +80 phase margin c load = 100pf, r load = 10k ? to 100k ? +40 d egr ees slew rate c load = 100pf 3.5 v/? input offset voltage v cm = 1.25v and 2.5v -3 +3 mv input leakage current -10 +10 na input common-mode range (cmvr) +0.50 v avl - 2.0 v common-mode rejection ratio (cmrr) 75 db drivers dh, dl break-before-make time c load = 2000pf 20 ns dh on-resistance in low state v bst - v lx = 5v 1.0 2.5 ? dh on-resistance in high state v bst - v lx = 5v 1.5 3.3 ? dl on-resistance in low state v vl = v v+ = 5v 0.45 1.0 ? dl on-resistance in high state v vl = v v+ = 5v 1.3 2.5 ? bst bias current v bst = 33v, v lx = 28v, v en = 0v 230 520 ? lx bias current v bst = 33v, v lx = 28v, v en = 0v -230 -520 ? bst/lx leakage current v bst = v lx = 28v, v en = 0v 50 ? logic inputs (en) input low level 4.5v < v vl = v v+ = v avl < 5.5v 1.14 0.80 v input high level 4.5v < v vl = v v+ = v avl < 5.5v 2.40 1.73 v input bias current v vl = v v+ = v avl = 5.5v, v en = 0 to 5.5v -1 +1 ?
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v v+ = v vl = v avl = v en = v refin = 5v, v bst = 6v, v lx = 1v, c vl = 4.7?, c refout = 1?, v ain- = v aout , v ain+ = 2.5v, v ilim = v lx - 0.2v, v fb = 0.65v, gnd = pgnd = 0v, c ss = 0.01?, r freq = 20k ? , t a = 0? to +85? , typical values are at t a = +25?, unless otherwise noted.) parameter conditions min typ max units refin input (MAX8597 only) refin input voltage range 0 2.75 v refin dual mode threshold v avl - 1.0 v avl - 0.5 v refin input bias current v refin = 1.25v or 2.5v -250 +250 na ov and uv fault comparators upper fb fault threshold (ov) rising edge, hysteresis = 15mv (max8599 only) 115 117 120 % lower fb fault threshold (uv) falling edge, hysteresis = 15mv 67 70 73 % power-ok output (pok) (max8598/max8599 only) pok delay for both fb rising and falling edges 8 clock cycles lower fb pok threshold fb falling, hysteresis = 20mv 85 88 90 % pok output low level i sink = 2ma 0.4 v pok output high leakage v pok = 5.5v 5 a electrical characteristics (v v+ = v vl = v avl = v en = v refin = 5v, v bst = 6v, v lx = 1v, c vl = 4.7?, c refout = 1?, v ain- = v aout , v ain+ = 2.5v, v ilim = v lx - 0.2v, v fb = 0.65v, gnd = pgnd = 0v, c ss = 0.01?, r freq = 20k ? , t a = -40? to +85? , typical values are at t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units general v+ operating range 5.5 28.0 v v+/vl operating range v+ = vl 4.5 5.5 v v+ operating supply current v v+ = 12v, vl unloaded, no mosfets connected, v fb = 0v 5.0 ma vl regulator output voltage 5.5v < v v+ < 28v, 1ma < i load < 35ma 4.7 5.3 v vl undervoltage-lockout trip level rising edge, typical hysteresis = 460mv 4.05 4.35 v reference (MAX8597 only) refout output voltage i refout = 150?, v v+ = v vl = 4.5v or 5.5v 2.47 2.51 v refout load regulation i refout = 10? to 1ma 10 mv current-limit comparator (all current limits are tested at v v+ = v vl = 4.5v and 5.5v) ilim sink current v ilim = v lx - 0.2v, 1.8v < v lx < 28v, v bst = v lx + 5v 180 220 ? comparator input offset voltage error -10 +10 mv soft-start soft-start source current v ss = 100mv 3 7 ? soft-start sink current v ss = (0.6v or v refin ) 3 7 ? dual mode is a trademark of maxim integrated products, inc.
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers _______________________________________________________________________________________ 5 electrical characteristics (continued) (v v+ = v vl = v avl = v en = v refin = 5v, v bst = 6v, v lx = 1v, c vl = 4.7?, c refout = 1?, v ain- = v aout , v ain+ = 2.5v, v ilim = v lx - 0.2v, v fb = 0.65v, gnd = pgnd = 0v, c ss = 0.01?, r freq = 20k ? , t a = -40? to +85? , typical values are at t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units frequency r freq = 100k ? 140 240 r freq = 20.0k ? 800 1200 frequency r freq = 14.3k ? 1100 1700 khz dh minimum off-time 180 230 ns dh minimum on-time 140 ns fb error amplifier fb input bias current 150 na fb input voltage set point over load and line 0.591 0.606 v fb offset error v refin = 1.25v and 2.5v, measured with respect to refin +20 -20 mv error-amp open-loop voltage gain v comp = 1.2v to 2.4v 72 db uncommitted operational amplifier (MAX8597 only) output voltage swing high v ain+ = 2.5v, v ain - = (v ain+ - 100mv), i source = 100? v avl - 20mv v output voltage swing low v ain+ = 2.5v, v ain - = (v ain+ + 100mv), i sink = 100? 20 mv input offset voltage v cm = 1.25v and 2.5v -3 +3 mv input common-mode range (cmvr) +0.50 v avl - 2.0 v drivers dh on-resistance in low state v bst - v lx = 5v 2.5 ? dh on-resistance in high state v bst - v lx = 5v 3.3 ? dl on-resistance in low state v vl = v v+ = 5v 1.0 ? dl on-resistance in high state v vl = v v+ = 5v 3.5 ? bst bias current v bst = 33v, v lx = 28v, v en = 0v 520 ? lx bias current v bst = 33v, v lx = 28v, v en = 0v -520 ? bst/lx leakage current v bst = v lx = 28v, v en = 0v 50 ? logic inputs (en) input low level 4.5v < v vl = v v+ = v avl < 5.5v 0.8 v input high level 4.5v < v vl = v v+ = v avl < 5.5v 2.4 v input bias current v vl = v v+ = v avl = 5.5v, v en = 0 to 5.5v -1 +1 ? refin input (MAX8597 only) refin input voltage range 0 2.75 v refin dual-mode threshold v avl - 1.0 v avl - 0.5 v refin input bias current v refin = 1.25v or 2.5v -250 +250 na
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers 6 _______________________________________________________________________________________ note 1: limits to -40? are guaranteed by design and characterization. electrical characteristics (continued) (v v+ = v vl = v avl = v en = v refin = 5v, v bst = 6v, v lx = 1v, c vl = 4.7?, c refout = 1?, v ain- = v aout , v ain+ = 2.5v, v ilim = v lx - 0.2v, v fb = 0.65v, gnd = pgnd = 0v, c ss = 0.01?, r freq = 20k ? , t a = -40? to +85? , typical values are at t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units ov and uv fault comparators upper fb fault threshold (ov) rising edge, hysteresis = 15mv (max8599 only) 115 120 % lower fb fault threshold (uv) falling edge, hysteresis = 15mv 67 73 % power-ok output (pok) (max8598/max8599 only) lower fb pok threshold fb falling, hysteresis = 20mv 85 90 % pok output low level i sink = 2ma 0.4 v pok output high leakage v pok = 5.5v 5 ? efficiency vs. load current circuit of figure 1 MAX8597 toc01 load current (a) efficiency (%) 1 65 70 75 80 85 90 95 100 60 0.1 10 v out = 11.5v v out = 9v v out = 6v efficiency vs. load current circuit of figure 2 MAX8597 toc02 load current (a) efficiency (%) 10 40 50 60 70 80 90 100 30 1100 v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.2v output voltage vs. load current MAX8597 toc03 i load (a) output voltage (v) 18 16 14 12 10 8 6 4 2 1.195 1.200 1.205 1.210 1.190 020 output voltage vs. input voltage MAX8597 toc04 v in (v) output voltage (v) 13.5 13.0 12.5 12.0 11.5 11.0 10.5 1.195 1.200 1.205 1.210 1.190 10.0 14.0 i load = 0a i load = 20a power-up waveforms MAX8597 toc05 2ms/div 5v/div v avl i lx v out v in 10a/div 1v/div 10v/div power-down waveforms MAX8597 toc06 2ms/div 5v/div v avl i lx i out v in 10a/div 1v/div 10v/div typical operating characteristics (circuit of figure 4, t a = +25?, 500khz switching frequency, v in = 12v, unless otherwise noted.)
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers _______________________________________________________________________________________ 7 output prebiased startup MAX8597 toc07 1ms/div 10v/div v lx v out v in v dl 1.0v 1.2v 5v/div 5v/div startup/shutdown with en (i load = 20a) MAX8597 toc08 2ms/div 5v/div v pok i lx v out v en 10a/div 1v/div 5v/div output voltage vs. v adj (v in = 12v) MAX8597 toc09 v adj (v) output voltage (v) 5 4 3 2 1 5 6 7 8 9 10 11 12 13 4 06 circuit of figure 1 r load = 1.2 ? entering dropout waveforms circuit of figure 1 MAX8597 toc10 2 s/div 10v/div v lx v out v comp v in (ac-coupled) 11v 500mv/div 100mv/div heavy-dropout waveforms circuit of figure 1 MAX8597 toc11 10 s/div 10v/div v lx v out v comp v in (ac-coupled) 11.9v 500mv/div 500mv/div output tracking refin MAX8597 toc12 1ms/div v refin v out 1v/div v refin v out 1v/div circuit of figure 3 5ms rise time 1ms rise time typical operating characteristics (continued) (circuit of figure 4, t a = +25?, 500khz switching frequency, v in = 12v, unless otherwise noted.)
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 4, t a = +25?, 500khz switching frequency, v in = 12v, unless otherwise noted.) 50% load step at 5a/ s MAX8597 toc13 40 s/div 50mv/div v out (ac-coupled) i out 20a 10a 90% load step at 5a/ s MAX8597 toc14 40 s/div 100mv/div v out (ac-coupled) i out 20a 2a short-circuit response MAX8597 toc15 4ms/div 1v/div 2a/div v out i in i lx 10a/div output overvoltage protection MAX8597 toc16 10 s/div 500mv/div 10v/div v fb v dh v dl 5v/div
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers _______________________________________________________________________________________ 9 control logic bias soft-start osc vl pgnd dl lx dh vl v+ vl refout (MAX8597) ss refin (MAX8597) fb ain- (MAX8597) ain+ (MAX8597) aout (MAX8597) comp gnd en freq avl bst ilim 200 a pwm reference ovp eamp 0.7 x v reg uvp n pok (max8598/ max8599) 1.17 x v reg (max8599) 0.88 x v reg 1/20 counter 1v p-p v reg MAX8597 max8598 max8599 block diagram
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers 10 ______________________________________________________________________________________ pin description pin MAX8597 max8598/ max8599 name function 1 1 avl filtered vl input. connect to vl through a 10 ? resistor. bypass to gnd with a 0.22? or larger ceramic capacitor. 2 refin external reference input. fb tracks the voltage input to refin. connect refin to avl to use the internal 0.6v reference. 3 2 gnd analog ground. connect to the exposed paddle and analog ground plane and then connect to pgnd at the output ground. 43ss soft-start programming input. connect a capacitor from ss to gnd to set the soft-start time. see the selecting the soft-start capacitor section for details. 54fb feedback input. connect to the center tap of an external resistor-divider to set the output voltage. regulates to 0.6v for the max8598/max8599 and MAX8597 when refin is connected to avl. regulates to v refin (MAX8597) when using an external reference. 65 comp compensation input. connect to the required compensation network. see the compensation design section for details. 7 6 en enable input. drive en high to enable the ic. drive low to shut down the ic. 8 refout internal reference output. refout regulates to 2.5v and can source up to 1ma. refout discharges to gnd during uvlo. 97v+ input supply voltage for internal vl regulator. connect to an input supply in the 4.5v to 28v range. bypass to gnd with a 1? or larger ceramic capacitor through a 3 ? resistor. 10 8 vl internal 5v linear-regulator output. vl provides power for the internal mosfet gate drivers. bypass to pgnd with a 1? or larger ceramic capacitor. vl is always enabled except in thermal shutdown. see the internal 5v linear regulator section for details. 11 9 dl low-side gate-driver output. connect to the gate of the synchronous rectifier. dl swings from pgnd to vl. dl is held low during shutdown. 12 10 pgnd power ground. connect to the synchronous rectifier? source and pgnd plane. 13 11 bst bootstrap input supply for the high-side mosfet driver. connect to the cathode of an external diode from vl and connect a 0.1? or larger capacitor from bst to lx. 14 12 dh high-side gate-driver output. connect to the gate of the high-side mosfet. dh swings from lx to bst. dh is low (connected to lx) during shutdown. 15 13 lx external inductor connection. lx is the low supply for the dh gate driver as well as the sense connection for the current-limit circuitry. connect lx to the switched side of the inductor as well as the source of the high-side mosfet and the drain of the synchronous rectifier. 16 14 ilim current-limit sense input. connect a resistor from ilim to the current-sense point to set the output current limit. see the setting the current limit section for details.
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ______________________________________________________________________________________ 11 pin description (continued) pin MAX8597 max8598/ max8599 name function 17 15 freq frequency adjust input. connect a resistor from freq to gnd to set the switching frequency. the range of the freq resistor is 14.3k ? to 100k ? (corresponding to 1400khz to 200khz). 18 aout output of the uncommitted operational amplifier. aout is high impedance during undervoltage lockout. 19 ain- inverting input of the uncommitted operational amplifier 20 ain+ noninverting input of the uncommitted operational amplifier ?6pok power-ok output. pok is an open-drain output that goes high impedance when the regulator output is greater than 88% of the regulation threshold. pok is low during shutdown. ep exposed paddle. connect to analog ground plane for improved thermal performance. detailed description the MAX8597/max8598/max8599 voltage-mode pwm step-down controllers are designed to operate from 4.5v to 28v input and generate output voltages down to 0.6v. a proprietary switching algorithm stretches the duty cycle to >99.5% for low-dropout design. unlike conventional step-down regulators using a p-channel high-side mosfet to achieve high duty cycle, the MAX8597/max8598/max8599 drive n-channel mosfets permitting high efficiency and high-current designs. the MAX8597 is available in a 20-pin thin qfn pack- age and is designed for applications that use an ana- log signal to control the output voltage with adjustable offset, such as dc fan speed control. for example, a 12vdc fan can be driven from 6v to 12v with 12v input power source depending on the system? cooling requirement to minimize fan noise and power consump- tion. this is achieved with an internal uncommitted operational amplifier. with the addition of an external rc filter, a pwm input can also be used to control the output voltage. the MAX8597 also generates a tracking output for chipsets, asics, and dsp where core and i/o supplies are split and require tracking. in applica- tions where tighter output tolerance is required, the MAX8597 output can be set by an external precision reference source feeding to refin. the max8598/ max8599 are available in a 16-pin thin qfn package and do not have the uncommitted operational amplifier, reference input, and reference output, but offer a power- ok output (pok). with the enable input and pok out- put, the max8598/max8599 can easily be configured to have power sequencing of multiple supply rails. the MAX8597/max8598/max8599 allow startup with prebias voltage on the output for applications where a backup supply or a tracking device may charge the output capacitor before the MAX8597/max8598/ max8599 are enabled. the max8599 has output over- voltage protection. these controllers feature lossless high-side peak inductor current sensing, adjustable current limit, and hiccup-mode short-circuit protection. switching fre- quency is set with an external resistor from 200khz to 1.4mhz. this wide frequency range combined with a wide-bandwidth error amplifier enable the loop-com- pensation scheme to give the user ample flexibility to optimize for cost, size, and efficiency. dc-dc controller the MAX8597/max8598/max8599 step-down dc-dc controllers use a pwm voltage-mode control scheme. an internal high-bandwidth (25mhz) operational amplifier is used as an error amplifier to regulate the output voltage. the output voltage is sensed and compared with an inter- nal 0.6v reference or refin (MAX8597) to generate an error signal. the error signal is then compared with a fixed-frequency ramp by a pwm comparator to give the appropriate duty cycle to maintain output voltage regula- tion. the high-side mosfet turns on at the rising edge of the internal clock 20ns after dl (the low-side mosfet gate drive) goes low. the high-side mosfet turns off once the internal ramp voltage reaches the error-amplifier output voltage. the process repeats for every clock cycle. during the high-side mosfet on-time, current flows from the input through the inductor to the output capacitor and load. at the moment the high-side mos- fet turns off, the energy stored in the inductor during the on-time is released to support the load as the inductor
MAX8597/max8598/max8599 current ramps down through the low-side mosfet body diode; 20ns after dh goes low, the low-side mosfet turns on, resulting in a lower voltage drop to increase effi- ciency. the low-side mosfet turns off at the rising edge of the next clock pulse, and when its gate voltage dis- charges to zero, the high-side mosfet turns on and another cycle starts. these controllers also sense peak inductor current and provide hiccup-overload and short-circuit protection (see the current limit section). the MAX8597/ max8598/max8599 operate in forced-pwm mode where the inductor current is always continuous. the controller maintains constant switching frequency under all loads, except under dropout conditions where it skips dl pulses. current limit the MAX8597/max8598/max8599 dc-dc step-down controllers sense the peak inductor current either with the on-resistance of the high-side mosfet for lossless sensing, or a series resistor for more accurate sensing. when the voltage across the sensing element exceeds the current-limit threshold set with ilim, the controller immediately turns off the high-side mosfet. the low- side mosfet is then turned on to let the inductor cur- rent ramp down. as the output load current increases above the ilim threshold, the output voltage sags because the truncated duty cycle is insufficient to sup- port the load current. when fb falls 30% below its nomi- nal threshold, the output undervoltage protection is triggered and the controller enters hiccup mode to limit power dissipation. this current-limit method allows the circuit to withstand a continuous output short circuit. the MAX8597/max8598/max8599 current-limit thresh- old is set by an external resistor that works in conjunc- tion with an internal 200? current sink (see the setting the current limit section for more details). synchronous-rectifier driver (dl) synchronous rectification reduces the conduction loss in the rectifier by replacing the normal schottky catch diode with a low-resistance mosfet switch. the MAX8597/max8598/max8599 also use the synchro- nous rectifier to ensure proper startup of the boost gate-drive circuit. high-side gate-drive supply (bst) gate-drive voltage for the high-side n-channel mosfet is generated by an external flying capacitor and diode boost circuit (d1 and c5 in figure 1). when the synchronous rectifier is on, c5 is charged from the vl supply through the schottky diode. when the synchronous rectifier is turned off, the schottky is reverse biased and the voltage on c5 is stacked above lx to provide the necessary turn- on voltage for the high-side mosfet. a low-current schottky diode, such as central semiconductor? cmdsh-3, works well for most applications. the capacitor should be large enough to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum low-side mosfet on-time, which occurs at minimum input voltage. a capacitor in the 0.1? to 0.47? range works well for most applications. internal 5v linear regulator the MAX8597/max8598/max8599 contain a low- dropout 5v regulator that provides up to 35ma to sup- ply gate drive for the external mosfets, and supplies avl, which powers the ic? internal circuitry. bypass the regulator? output (vl) with 1? per 10ma of vl load, or greater ceramic capacitor. the current required to drive the external mosfet can be estimat- ed by multiplying the total gate charge (at v gs = 5v) of the mosfets by the switching frequency. undervoltage lockout (uvlo) when v vl drops below 3.75v (typ), the MAX8597/ max8598/max8599s?undervoltage-lockout (uvlo) cir- cuitry inhibits switching, forces pok (max8598/ max8599) low, and forces dh and dl low. once v vl rises above 4.2v (typ), the controller powers up the out- put in startup mode (see the startup section). startup the MAX8597/max8598/max8599 start switching once all the following conditions are met: 1) en is high. 2) v vl > 4.2v (typ). 3) soft-start voltage v ss exceeds v fb . 4) thermal limit is not exceeded. the third condition ensures that the MAX8597/ max8598/max8599 do not discharge a prebiased out- put. once all of these conditions are met, the ic begins switching and the soft-start cycle is initiated. low-dropout, wide-input-voltage, step-down controllers 12 ______________________________________________________________________________________
power-ok signal (pok, max8598/max8599 only) the power-ok signal (pok) is an open-drain output that goes high impedance when fb is above 91% of its nom- inal threshold. there is an eight clock-cycle delay before pok goes high impedance. for 500khz switching fre- quency, this delay is typically 16?. to obtain a logic voltage output, connect a pullup resistor from pok to avl. a 100k ? resistor works well for most applications. if unused, connect pok to gnd or leave it unconnected. enable and soft-start the MAX8597/max8598/max8599 are enabled using the en input. a logic high on en enables the output of the ic. conversely, a logic low on en disables the out- put. on the rising edge of en, the controllers enter soft- start. soft-start gradually ramps up the reference voltage seen at the error amplifier to control the output rate of rise and reduce the inrush current during start- up. the soft-start period is determined by a capacitor connected from ss to gnd (c6 in figure 1). a 5? cur- rent source charges the external capacitor to the refer- ence voltage (0.6v or v refin ). the capacitor value is determined as follows: where t ss is the soft-start time in seconds and v fb is 0.6v or v refin . the output reaches regulation when soft-start is completed. output undervoltage protection (uvp) output uvp begins when the controller is at its current limit and v fb is 30% below its nominal threshold. this condition causes the controller to drive dh and dl low and discharges the soft-start capacitor with a 5? pull- down current until v ss reaches 50mv. then the con- troller begins in soft-start mode. if the overload condition still exists, the uvp process begins again. the result is ?iccup?mode, where the controller attempts to restart periodically as long as the overload condition exists. in hiccup mode, the soft-start capacitor voltage ramps up to 112% of the nominal v fb threshold and then ramps down to 50mv. for the MAX8597, v refin must be greater than 450mv to trigger uvp. the soft- start capacitor voltage then ramps up to 112% of v refin and then down to 50mv. output overvoltage protection (ovp, max8599) the output voltage is continuously monitored for over- voltage (max8599 only). if the output voltage is more than 117% of its nominal set value, ovp is triggered after a 12? (typ) delay. the max8599 latches dh low to turn off the high-side mosfet, and dl high to turn on the low-side mosfet to clamp the output to pgnd. the latch is reset either by toggling en or by cycling v+ below the uvlo threshold. note that dl latching high causes a negative spike at the output due to the energy stored in the output lc at the instant of ovp trip. if the load cannot tolerate this negative spike, add a power schottky diode across the output to act as a reverse polarity clamp. thermal-overload protection thermal-overload protection limits the total power dissi- pation in the MAX8597/max8598/max8599. when the junction temperature exceeds +160?, a thermal sen- sor shuts down the device, forcing dh and dl low, allowing the ic to cool. the thermal sensor turns the part on after the junction temperature cools by 10?, resulting in a pulsed output during continuous thermal- overload conditions. during a thermal event, the switch- ing converter is turned off, the reference is turned off, the vl regulator is turned off, pok is high impedance, and the soft-start capacitor is discharged. c at v ss fb 6 5 = MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ______________________________________________________________________________________ 13
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers 14 ______________________________________________________________________________________ MAX8597 gnd comp refo fb vl dl lx dh bst ss 19 20 18 5 3 1810 11 15 14 13 vl vl c5 0.22 f c7a 47 f c7b 47 f c12 4.7 f d1 cmdsh-3 q2 irf7821 q1 irf7821 l1 1 h ain- v in (10.8v to 13.2v) v out 6v to 12v/10a en on off c1 1 f c3 0.01 f c6 0.033 f c9 820pf c8 4.7pf c10 100pf r1 33.2k ? r2 1.21k ? r11 5.1k ? r8 24.9k ? r9 6.04k ? r10 93.1k ? avl r12 47k ? c2a 10 f c2b 10 f pgnd 4 12 6 aout r13 10 ? r16 3 ? avl ain+ v adj (0v to 5v) r4 100k ? r5 32.4k ? r6 48.7k ? r7 48.7k ? c13 1 f r1 2 ? c14 2200pf r15 3 ? c15 0.01 f 2 7 17 9 16 refin en freq v+ ilim c11 0.22 f figure 1. MAX8597 (600khz): live adjustable output voltage from 6v to 12v at 10a figure 2. 1.2v at 20a output with remote sensing MAX8597 gnd comp refo fb vl dl lx dh bst ss 19 20 18 5 3 1810 11 15 14 13 vl vl c7a 470 f c7b 470 f c12 4.7 f d1 cmdsh-3 l1 0.7 h ain- v in (10.8v to 13.2v) v out 1.2v/20a en on off c1 1 f c3 0.01 f c4 0.033 f c9 6800pf c8 39pf c8 1800pf r1 40.2k ? r2 1.65k ? r8 7.2k ? r7 12.1k ? r6 10k ? avl r10 16k ? c2a 10 f c2c 10 f c2b 10 f pgnd 4 12 6 aout r11 10 ? avl ain+ r3 10k ? r4 10k ? r5 10k ? r9 12.1k ? c11 1 f r12 3 ? c13 2200pf r14 3 ? 2 7 17 9 16 refin en freq v+ ilim c10 0.22 f q2 q1 q4 q3 (q3 = q4 = irf7832) (q1 = q2 = irf7807z) r16 3 ? c5 0.22 f design procedure
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ______________________________________________________________________________________ 15 MAX8597 gnd comp refo fb vl dl lx dh bst ss 19 20 18 5 3 1810 11 15 14 13 vl vl c5 0.22 f c7a 100 f c7b 100 f c13 4.7 f d1 cmdsh-3 q2 irf7821 q1 irf7807z l1 0.56 h ain- v in (10.8v to 13.2v) v out 1.8v/10a en on off c1 1 f c3 0.01 f c6 2200pf c9 8200pf c8 56pf c10 1000pf r1 20k ? r2 1.5k ? r7 390 ? r6 10k ? avl r8 5.6k ? c2a 10 f c2b 10 f pgnd 4 12 6 aout r9 10 ? ain+ c12 1 f r10 2 ? c14 2200pf r12 3 ? 2717 9 16 refin en freq v+ ilim c11 0.22 f c4 1000pf r3 70 k ? r4 18.2 k ? r5 6.98 k ? d2 cmpd914 refin r16 3 ? figure 3. MAX8597 1mhz tracking supply with clamp (output voltage tracks v refin from 0v up to the nominal output regulation voltage.) max8598 max8599 gnd fb pgnd dl lx dh bst 16 3 5 4 2 110 9 13 12 11 vl c7a 470 f c7b 470 f c11 4.7 f d1 cmdsh-3 l1 0.7 h pok v in (10.8v to 13.2v) v out 1.2v/20a en pok on off c1 1 f c3 0.01 f c4 0.033 f c9 6800pf c8 39pf c8 1800pf r1 40.2k ? r2 2.26k ? r6 1.2k ? r5 12.1k ? avl 8 vl r7 16k ? c2a 10 f c2c 10 f c2b 10 f comp r8 10 ? ss r4 12.1k ? r9 3 ? c12 2200pf r11 3 ? 6157 14 en freq v+ ilim c10 0.22 f q2 hat2165h q3 hat2165h q1 hat2168h avl r3 100 k ? avl vl r16 3 ? c5 0.22 f figure 4. max8598/max8599 500khz, 1.2v, 20a output power supply design procedure (continued)
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers 16 ______________________________________________________________________________________ setting the output voltage fixed output voltage the output voltage is set by a resistor-divider network from the output to gnd with fb at the center tap (r4 and r5 in figure 4). select r4 between 5k ? and 15k ? and calculate r5 by: r5 = r4 x [( v out / v fb ) - 1] live adjustable output voltage (see figure 1) using the uncommitted operational amplifier, the MAX8597 can be configured such that the output volt- age is adjustable using a voltage source (v adj ). the following parameters must be defined before starting the design: ? the minimum desired output voltage, v out_min ? the maximum desired output voltage, v out_max ? the desired input that corresponds to the minimum output voltage, v adj_min ? the desired input that corresponds to the maximum output voltage, v adj_max select v aout (uncommitted operational-amplifier out- put) between 0.05v and 3v and v aout_max higher than v aout_min . calculate the required ain+ reference (v ain+ ) as: v ain+ is set using a resistor-divider from refout to gnd (r6 and r7). select r7 to be approximately 50k ? as a starting point and then calculate r6 as: r6 = r7 x [(2.5v / v ain+ ) - 1] select r4 to be 100k ? and calculate r5 as: select r9 between 5k ? and 15k ? , then calculate r8 and r10 as follows: where v fb is the feedback regulation voltage (0.6v with refin connected to avl). additionally, to minimize error, r6 and r7 should be chosen such that: inductor selection there are several parameters that must be examined when determining which inductor is to be used: input voltage, output voltage, load current, switching fre- quency, and lir. lir is the ratio of inductor current rip- ple to dc load current. a higher lir value allows for a smaller inductor but results in higher losses and higher output ripple. a good compromise between size and efficiency is a 30% lir. once all the parameters are chosen, the inductor value is determined as follows: where f s is the switching frequency. choose a standard value close to the calculated value. the exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost, but also increase the output ripple and reduce the efficiency due to higher peak currents. on the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower ac current levels. find a low- loss inductor having the lowest possible dc resistance that fits the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well up to 300khz. the chosen inductor? saturation current rating must exceed the peak inductor current determined as: input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit? switching. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents defined by the following equation: i ivvv v rms load out in out in = () ? ii lir i peak load max load max =+ ? ? ? ? ? ? () () 2 l vxvv v x f x i x lir out in out in s load max () = () ? rr rr rr rr 67 67 45 45 + = + r rr v v vr vv r out max fb fb fb aout min 10 89 89 _ _ = () () + () [] ? ? r vvvv v vv v vvvvv r out min fb fb aout min out max fb aout max fb out max fb out min fb fb 8 9 ____ __ = () () + () () [ ] ()() () ?? ? ? ?? ? r vv r vv ain aout min adj max ain 5 4 ( ) ( ) _ _ = + + ? ? v vvvv vv v v ain aout max adj max aout min adj min adj max adj min aout max aout min + = + ? ?? ()( ) __ __ __ _ _
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ______________________________________________________________________________________ 17 i rms has a maximum value when the input voltage equals twice the output voltage (v in = 2 x v out ), so i rms(max) = i load / 2. ceramic capacitors are recom- mended due to their low esr and esl at high frequen- cy, with relatively lower cost. choose a capacitor that exhibits less than 10? temperature rise at the maximum operating rms current for optimum long-term reliability. output capacitor the key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (esr), the equivalent series inductance (esl), and the voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. the output ripple has three compo- nents: variations in the charge stored in the output capacitor, voltage drop across the capacitor? esr, and voltage drop across the capacitor? esl, caused by the current into and out of the capacitor. the follow- ing equations estimate the worst-case ripple: where i p-p is the peak-to-peak inductor current. the response to a load transient depends on the select- ed output capacitor. after a load transient, the output instantly changes by (esr x ? i load ) + (esl x di/dt). before the controller can respond, the output deviates further depending on the inductor and output capacitor values. after a short period of time (see the typical operating characteristic s), the controller responds by regulating the output voltage back to its nominal state. the controller response time depends on the closed- loop bandwidth. with higher bandwidth, the response time is faster, preventing the output capacitor voltage from further deviation from its regulation value. do not exceed the capacitor? voltage or ripple current ratings. mosfet selection the MAX8597/max8598/max8599 controllers drive external, logic-level, n-channel mosfets as the circuit- switch elements. the key selection parameters are: ? on-resistance (r ds(on) ): the lower, the better. ? maximum drain-to-source voltage (v dss ): should be at least 20% higher than the input supply rail at the high-side mosfet? drain. ? gate charges (q g , q gd , q gs ): the lower, the better. choose mosfets with r ds(on) rated at v gs = 4.5v. for a good compromise between efficiency and cost, choose the high-side mosfet that has conduction loss equal to the switching loss at the nominal input voltage and maximum output current. for the low-side mosfet, make sure it does not spuriously turn on due to dv/dt caused by the high-side mosfet turning on, resulting in efficiency degrading shoot-through current. mosfets with a lower q gd /q gs ratio have higher immunity to dv/dt. for proper thermal-management design, the power dis- sipation must be calculated at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for low-side mosfet, worst case is at v in(max) ; for high-side mosfet, it could be either at v in(min) or v in(max) ). high-side and low-side mosfets have different loss components due to the circuit operation. the low-side mosfet operates as a zero-voltage switch; therefore, the major losses are the channel-conduction loss (p lscc ) and the body-diode conduction loss (p lsdc ): p lscc = [1 - (v out / v in )] x (i load ) 2 x r ds(on) p lsdc = 2 x i load x v f x t dt x f s where v f is the body-diode forward-voltage drop, t dt is the dead-time between the high-side mosfet and the low-side mosfet switching transitions, and f s is the switching frequency. the high-side mosfet operates as a duty-cycle control switch and has the following major losses: the channel-conduction loss (p hscc ), the v-i overlapping switching loss (p hssw ), and the drive loss (p hsdr ). the high-side mosfet does not have body-diode conduction loss because the diode never conducts current: p hscc = (v out / v in ) x i load 2 x r ds(on) use r ds(on) at t j(max) : p hssw = v in x i load x f s x [(q gs + q gd ) / i gate ] where i gate is the average dh-high driver output-cur- rent capability determined by: i gate = 2.5 / (r dh + r gate ) vv v v v i esr v v esl l esl v i cf i vv fl v v ripple ripple esr ripple esl ripple c ripple esr p p ripple esl in ripple c pp out s pp in out s out in =++ = = + = = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () () () () () 8
MAX8597/max8598/max8599 where r dh is the high-side mosfet driver? average on-resistance (1.25 ? typ) and r gate is the internal gate resistance of the mosfet (typically 0.5 ? to 2 ? ): p hsdr = q gs x v gs x f s x r gate / (r gate + r dh ) where v gs ~ v vl = 5v. in addition to the losses above, add approximately 20% more for additional losses due to mosfet output capacitances and low-side mosfet body-diode reverse-recovery charge dissipated in the high-side mosfet that exists, but is not well defined in the mosfet data sheet. refer to the mosfet data sheet for thermal-resistance specification to calculate the pc board area needed to maintain the desired maxi- mum operating junction temperature with the above- calculated power dissipation. to reduce emi caused by switching noise, add a 0.1? or larger ceramic capacitor from the high-side switch drain to the low- side switch source or add resistors in series with dh and dl to slow down the switching transitions. however, adding a series resistor increases the power dissipation of the mosfets, so be sure this does not overheat the mosfets. the minimum load current must exceed the high-side mosfet? maximum leakage plus the maximum lx bias current over temperature. setting the current-limit the MAX8597/max8598/max8599 controllers sense the peak inductor current to provide constant-current and hiccup current limit. the peak current-limit thresh- old is set by an external resistor (r2 in figure 1) togeth- er with the internal current sink of 200?. the voltage drop across the resistor r2 due to the 200? current sets the maximum peak inductor current that can flow through the high-side mosfet or the optional current- sense resistor (between the high-side mosfet source and lx) by the equations below: i peak(max) = 200? x r2 / r dson(hsfet) i peak(max) = 200? x r2 / r sense the actual corresponding maximum load current is lower than the i peak(max) by half of the inductor ripple current. if the r ds(on) of the high-side mosfet is used for current sensing, use the maximum r ds(on) at the highest operating junction temperature to avoid false tripping of the current limit at elevated temperature. consideration should also be given to the tolerance of the 200? current sink. when the r ds(on) of the high- side mosfet is used for current sensing, ringing on the lx voltage waveform can interfere with the current limit. below is the procedure for selecting the value of the series rc snubber circuit (r14 and c14 in figure 1): 1) connect a scope probe to measure v lx to gnd, and observe the ringing frequency, f r . 2) find the capacitor value (connected from lx to gnd) that reduces the ringing frequency by half. the circuit parasitic capacitance (c par ) at lx is then equal to 1/3 the value of the added capaci- tance above. the circuit parasitic inductance (l par ) is calculated by: the resistor for critical dampening (r14) is equal to 2 x f r x l par . adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. the capacitor (c14) should be at least 2 to 4 times the value of the c par in order to be effective. the power loss of the snubber circuit is dissipated in the resistor (r14) and is calculated as: p r14 = c14 x (v in ) 2 x f s where v in is the input voltage and f s is the switching frequency. choose an r14 power rating that meets the specific application? derating rule for the power dissi- pation calculated. additionally, there is parasitic inductance of the cur- rent-sensing element, whether the high-side mosfet (l sense_fet ) or the optional current-sense resistor (l rsense ) are used, which is in series with the output filter inductor. this parasitic inductance, together with the output inductor, forms an inductive divider and causes error in the current-sensing voltage. to com- pensate for this error, a series rc circuit can be added in parallel with the sensing element (see figure 5). the rc time constant should equal l rsense / r sense , or l sense_fet / r ds(on) . first, set the value of r equal to or less than r2 / 100. then, the value of c is calculated as: c = l rsense / (r sense x r) or c = l sense_fet / (r ds(on) x r) any pc board trace inductance in series with the sens- ing element and output inductor should be added to the specified fet or resistor inductance per the respective manufacturer? data sheet. for the case of l fc par r par = () 1 2 2 low-dropout, wide-input-voltage, step-down controllers 18 ______________________________________________________________________________________
the mosfet, it is the inductance from the drain to the source lead. alternately, to save board space and cost, the rc net- works above can be omitted; however, the value of r ilim should be raised to account for the voltage step caused by the inductive divider. an additional switching noise filter may be needed at ilim by connecting a capacitor in parallel with r2 (in the case of r ds(on) sensing) or from ilim to lx (in the case of resistor sensing). for the case of r ds(on) sens- ing, the value of the capacitor should be: c3 > 15 / ( x f s x r2) for the case of resistor sensing: c3 < 25 x 10 -9 / r2 selecting the soft-start capacitor an external capacitor from ss to gnd is charged by an internal 5? current source, to the corresponding feed- back threshold. therefore, the soft-start time is calculat- ed as: t ss = c ss x v fb / 5? for example, 0.033? from ss to gnd yields approxi- mately a 3.96ms soft-start period. in the tracking application (see figure 3), the output voltage is required to track refin during refin rise and fall time. c ss must be chosen so that t ss is less than refin rise and fall time. compensation design the MAX8597/max8598/max8599 use a voltage-mode control scheme that regulates the output voltage by comparing the error-amplifier output (comp) with a fixed internal ramp to produce the required duty cycle. the error amplifier is an operational amplifier with 25mhz bandwidth to provide fast response. the output lowpass lc filter creates a double pole at the resonant frequency that introduces a gain drop of 40db per decade and a phase shift of 180 degrees per decade. the error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. the type iii compensation scheme (figure 6) is used to achieve this stability. the basic regulator loop can be thought of as consist- ing of a power modulator and an error amplifier. the power modulator has a dc gain set by v in / v ramp , with a double pole, f p_lc , and a single zero, f z_esr , set by the output inductor (l), the output capacitor (c o ), and its equivalent series resistance (r esr ). below are the equations that define the power modulator: where c o is the total output capacitance and r esr is the total esr of the output capacitors. g v v where v v typ f lc f rc mod dc in ramp ramp plc o z esr esr o () _ _ , ( ) == = = 1 1 2 1 2 MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ______________________________________________________________________________________ 19 r2 c3 r c r ds(on) dl lx dh ilim r2 r c r sense dl lx dh ilim c3 figure 5. adding rc for more accurate sensing
MAX8597/max8598/max8599 when the output capacitor is comprised of paralleling n number of the same capacitors, then: c o = n x c each and r esr = r esr_each / n thus, the resulting f z_esr is the same as that of a sin- gle capacitor. the total closed-loop gain must be equal to unity at the crossover frequency, where the crossover frequency is less than or equal to 1/5 the switching frequency (f s ): f c f s / 5 so the loop-gain equation at the crossover frequency is: g ea(fc) x g mod(fc) = 1 where g ea(fc) is the error-amplifier gain at f c , and g mod(fc) is the power-modulator gain at f c . the loop compensation is affected by the choice of out- put filter capacitor due to the position of its esr-zero frequency with respect to the desired closed-loop crossover frequency. ceramic capacitors are used for higher switching frequencies and have low capaci- tance and low esr; therefore, the esr-zero frequency is higher than the closed-loop crossover frequency. electrolytic capacitors (e.g., tantalum, solid polymer, and os-con) are needed for lower switching frequen- cies and have high capacitance (and some have high- er esr); therefore, the esr-zero frequency can be lower than the closed-loop crossover frequency. thus, the compensation design procedures are separated into two cases: case 1: crossover frequency is less than the out- put-capacitor esr-zero (f c < f z_esr ). the modulator gain at f c is: g mod(fc) = g mod(dc) x (f p_lc / f c ) 2 since the crossover frequency is lower than the output capacitor esr-zero frequency and higher than the lc double-pole frequency, the error-amplifier gain must have a +1 slope at f c so that, together with the -2 slope of the lc double pole, the loop crosses over at the desired -1 slope. the error amplifier has a dominant pole at a very low frequency (~0hz), and two additional zeros and two additional poles as indicated by the equations below and illustrated in figure 7: f z1_ea = 1 / (2 x r4 x c2) f z2_ea = 1 / (2 x (r1 + r3) x c1) f p2_ea = 1 / (2 x r3 x c1) f p3_ea = 1 / (2 x r4 x (c2 x c3 / (c2 + c3))) note that f z2_ea and f p2_ea are chosen to have the converter closed-loop crossover frequency, f c , occur when the error-amplifier gain has +1 slope, between f z2_ea and f p2_ea . the error-amplifier gain at f c must meet the requirement below: g ea(fc) = 1 / g mod(fc) the gain of the error amplifier between f z1_ea and f z2_ea is: g ea(fz1_ea - fz2_ea) = g ea(fc) x f z2_ea / f c = f z2_ea / (f c x g mod(fc) ) this gain is set by the ratio of r4/r1 (figure 6), where r1 is calculated as illustrated in the setting the output voltage section. thus: r4 = r1 x f z2_ea / (f c x g mod(fc) ) where f z2_ea = f p_lc . due to the underdamped (q > 1) nature of the output lc double pole, the first error-amplifier zero frequency must be set less than the lc double-pole frequency in order to provide adequate phase boost. set the error- amplifier first zero, f z1_ea , at 1/4 of the lc double-pole frequency. hence: c2 = 2 / ( x r4 x f p_lc ) set the error amplifier f p2_ea at f z_esr and the error-amplifier gain between f p2_ea and f p3_ea is set by the ratio of r4/rm and is equal to: g ea(fz1_ea - fz2_ea) x (f p2_ea / f p_lc ) where rm = r1 x r3 / (r1 + r3). then: rm = r4 x f p_lc / (g ea(fz1_ea - fz2_ea) x f p2_ea ) = r4 x f c x g mod(fc) / f p2_ea the value of r3 can then be calculated as: r3 = r1 x rm / (r1 ?rm) now we can calculate the value of c1 as: c1 = 1 / (2 x r3 x f p2_ea ) and c3 as: c3 = c2 / ((2 x c2 x r4 x f p3_ea ) - 1) fat f if f is less than f if f is greater than f then set fat f and f at f pea s z esr s z esr s pea s p ea z esr 3 23 22 2 2 __ _ ___ . , . low-dropout, wide-input-voltage, step-down controllers 20 ______________________________________________________________________________________
case 2: crossover frequency is greater than the output-capacitor esr zero (f c > f z_esr ). the modulator gain at f c is: g mod(fc) = g mod(dc) x (f p_lc ) 2 / (f z_esr x f c ) since the output-capacitor esr-zero frequency is high- er than the lc double-pole frequency but lower than the closed-loop crossover frequency, where the modu- lator already has -1 slope, the error-amplifier gain must have zero slope at f c so the loop crosses over at the desired -1 slope. the error-amplifier circuit configuration is the same as case 1 above; however, the closed-loop crossover fre- quency is now between f p2 and f p3 as illustrated in figure 8. the equations that define the error amplifier? zeros (f z1_ea , f z2_ea ) and poles (f p2_ea , f p3_ea ) are the same as case 1; however, f p2_ea is now lower than the closed-loop crossover frequency. therefore, the error- amplifier gain between f z1_ea and f z2_ea is now calcu- lated as: g ea(f z1_ea - f z2_ea ) = g ea(fc) x f z2_ea / f p2_ea = f z2_ea / (f p2_ea x g mod(fc) ) this gain is set by the ratio of r4/r1, where r1 is calcu- lated as illustrated in the setting the output voltage section. thus: r4 = r1 x f z2_ea / (f p2_ea x g mod(fc) ) where f z2_ea = f p_lc and f p2_ea = f z_esr . similar to case 1, c2 is calculated as: c2 = 2 / ( x r4 x f p_lc ) set the error-amplifier third pole, f p3_ea , at half the switching frequency, and let rm = (r1 x r3) / (r1 + r3). the gain of the error amplifier between f p2_ea and f p3_ea is set by the ratio of r4/rm and is equal to g ea(fc) = 1 / g mod(fc) . then: rm = r4 x g mod(fc) similar to case 1, r3, c1, and c3 are calculated as: r3 = r1 x rm / (r1 - rm) c1 = 1 / (2 x r3 x f z _esr) c3 = c2 / ((2 x c2 x r4 x f p3_ea ) - 1) MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ______________________________________________________________________________________ 21 MAX8597 max8598 max8599 fb comp c3 c2 r4 r2 r1 c1 r3 l c o ref figure 6. type iii compensation network gain (db) frequency 0 f z1 f z2 f p2 f c f p3 ea gain closed-loop gain figure 7. closed-loop and error-amplifier gain plot for case 1 gain (db) frequency 0 f z1 f z2 f p2 f c f p3 ea gain closed-loop gain figure 8. closed-loop and error-amplifier gain plot for case 2
MAX8597/max8598/max8599 applications information pc board layout guide careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. follow these guidelines for good pc board layout: 1) place the high-side mosfet close to the low-side mosfet and arrange them in such a way that the drain of the high-side mosfet and the source of the low-side mosfet can be tightly decoupled with a 10? or larger ceramic capacitor. the mosfets should also be placed close to the controller ic, preferably not more than 1.5in away from the ic. 2) place the ic? pin decoupling capacitors as close to pins as possible. 3) a current-limit setting resistor must be connected from ilim directly to the drain of the high-side mosfet. 4) try to keep the lx node connection to the ic pin separate from the connection to the flying boost capacitor. 5) keep the power ground plane (connected to the source of the low-side mosfet, pgnd pin, input and output capacitors?ground, vl decoupling ground) and the signal ground plane (connected to gnd pin and the rest of the circuit ground returns) separate. connect the two ground planes together at the ground of the output capacitor(s). 6) place the rc snubber circuit as close to the low- side mosfet as possible. 7) keep the high-current paths as short as possible. 8) connect the drains of the mosfets to a large cop- per area to help cool the devices and further improve efficiency and long-term reliability. 9) ensure the feedback connection is short and direct. place the feedback resistors as close to the ic as possible. 10) route high-speed switching nodes, such as lx, dh, and dl away from sensitive analog areas (fb, comp, ilim, ain+, ain-). refer to the MAX8597/max8598/max8599 evalua- tion kit for a sample board layout. low-dropout, wide-input-voltage, step-down controllers 22 ______________________________________________________________________________________ chip information transistor count: 4493 process: bicmos 1 avl 2 3 gnd ss 4 fb 12 dh 11 bst 10 pgnd 9 dl 5 comp 6 en 7 v+ 8 vl 16 pok 15 freq 14 ilim 13 lx max8598 max5899 thin qfn 4mm x 4mm top view pin configurations (continued)
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers ______________________________________________________________________________________ 23 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps c 1 2 21-0139 package outline 12, 16, 20, 24l thin qfn, 4x4x0.8mm
MAX8597/max8598/max8599 low-dropout, wide-input-voltage, step-down controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) c 2 2 21-0139 package outline 12, 16, 20, 24l thin qfn, 4x4x0.8mm

▲Up To Search▲

Price & Availability of MAX8597

	To Download MAX8597 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .